Register File
Storage of temporary data
Implementation of a RISC-V Processor
A RV32I Single Cycle CPU
Instruction Memory
Storage of executable program instructions
Data Memory
Storage of data during program execution
Register File
Storage of temporary data
Arithmetic Logic Unit
The Brain's Calculator
Branch Unit
To Branch or not to Branch, that is the Question
Sign Extension Unit
Bridging Data Sizes, Ensuring Accurate Interpretations!
Decoder
The Instruction Interpreter, Transforming Codes into Action
Final RISC-V CPU
Connect everything together